RISC-V VLSI Implementation Flow: RTL2GDS

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Principal Coordinator :
  • Dr. Gaurav Trivedi, IIT Guwahati
  • Co-Principal Coordinator :
  • Dr. Pankaj Kumar, NIT Patna
  • Dr. Sangeeta Singh, NIT Patna
  • Dr. C. Periasamy, MNIT Jaipur

  • Course Fee Details:


    Academic (student/faculty): 500 INR
    Industry People/ Others : 1000 INR
    Foreign Participants: 4000 INR

    Payment Details:
    Bank Name: Allahabad Bank (Merge to Indian Bank)
    Account Name: NIT Patna
    Account No.: 50380476798
    IFSC Code: IDIB000B810


    Resource Persons:

    EXPERTS/SPEAKERS - Prof. M. Balakrishnan, Prof. Anshul Kumar, IIT Delhi, Prof. Preeti Ranjan Panda, IIT Delhi; Prof. V. Kamakoti, IITM (consent awaited); Mr. Gaurav Jalan, Founder SpicaWorks, Bengaluru
    Open source-based design flow talks are all industry speaker-driven.


    Course contents:


    MODULES TOPICS :

    · Transistor to Processor Level Simulation and Verification

    · Digital Blocks constituting RISCV Processor

    · Digital Design to Processor ISA

    · RISCV Instruction Set Architecture

    · ISA Simulators

    · Simulation and Verification of RISCV ISA

    · RISCV Processor Design from Ground Up

    · Visualization of Processor blocks via Synthesis

    · Overview of RTL2GDS flow in processor design

    · Tapeout SignOff for Processor: What does it mean?

    · Power Performance Area Tradeoffs in RISCV Processor Design

    · RISC V Job Market

    All Modules will be covered using hands-on tutorials of RISC-V implementation in open source tool flow.


    Core Team Members, E&ICT Academy, NIT Patna:

    Dr. Bharat Gupta( CI E & ICT Academy,NIT Patna)
    Email: bharat@nitp.ac.in

    Dr. M.P Singh ( CO-CI E & ICT Academy,NIT Patna)
    Email: mps@nitp.ac.in

    Website: http://old.nitp.ac.in/ict/index.php



    Contact us :
    Electronics and ICT Academy
    National Institute of Technology, Patna
    AshokRajpath, Patna 800005
    Email: eictapatna@nitp.ac.in
    Website: http://old.nitp.ac.in/ict